`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
*                                                                             *
* Copyright (c) 2012 Andrew D. Zonenberg                                      *
* All rights reserved.                                                        *
*                                                                             *
* Redistribution and use in source and binary forms, with or without modifi-  *
* cation, are permitted provided that the following conditions are met:       *
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*                                                                             *
*    * Neither the name of the author nor the names of any contributors may be*
*      used to endorse or promote products derived from this software without *
*      specific prior written permission.                                     *
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED *
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******************************************************************************/

/**
	@file TopLevel.v
	@author Andrew D. Zonenberg
	@brief Top-level module of the CPLD
 */
module TopLevel(
	clk_20mhz,
	reset_in_n, uart_reset_n, prog_b_n, ethclken,
	cpld_miso, cpld_mosi,
	gpio
    );
	 
	////////////////////////////////////////////////////////////////////////////////////////////////
	// IO / parameter declarations
	input wire clk_20mhz;
	
	input wire reset_in_n;
	
	output wire uart_reset_n;
	output wire prog_b_n;
	output wire ethclken;
	
	output wire cpld_miso;
	input wire cpld_mosi;
	
	inout wire[9:0] gpio;
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Fillers for not-yet-used pins
	assign gpio = 10'bzzzzzzzzzz;
	assign cpld_miso = 0;
	assign uart_reset_n = 1'b1;
	assign ethclken = 1'b1;
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Clock division
	// Turn 20 Mhz into 20 KHz
	
	reg[9:0] clkdiv = 0;
	reg clk_20khz_edge = 0;							//asserted for one clk_20mhz cycle every 1024 cycles
	always @(posedge clk_20mhz) begin
		clkdiv <= clkdiv + 1;
		clk_20khz_edge <= 0;
		if(clkdiv == 0)
			clk_20khz_edge <= 1;
	end
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Switch debouncing
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// Global reset

	SwitchDebouncer #(.INIT_VAL(1)) reset_debouncer (
		.clk(clk_20mhz), 
		.clken(clk_20khz_edge), 
		.din(reset_in_n), 
		.dout(prog_b_n)
		);

	
endmodule
